The present invention relates to a semiconductor integrated circuit and a method of designing the same.
A functional block used for a system LSI is registered as a design asset or intellectual property (IP) in a library for reuse when a system LSI is newly designed. This type of functional block is called an IP block. The IP block is also called a virtual component (VC) such as an actual component on print-circuit boards.
The functional block includes a hard virtual component (HVC) of which the contents can be handled as a black box. Different from a soft virtual component (SVC) and a firm virtual component (FVC), the hard virtual component (HVC) is provided as polygon data, which has the disadvantages of design inflexibility and difficult process transplantation, but the advantage of capability of precisely estimating performance and physical dimensions.
Because of the limitations to performance such as integrity, speed, and power consumption of the functional block itself, input-output terminals of the functional block which can be handled as a black box are provided with routing as described below.
FIG. 10 shows an internal layout of a conventional functional block.
A functional block 20 has macrocells 30 to 33, input-output terminals 150 to 153, and multi-layer wirings 200 to 203 inside the functional block.
The macrocell 30 is connected to the input-output terminal 150 via the multi-layer wiring 200. In the same way, the macrocell 31 is connected to the input-output terminal 151 via the multi-layer wiring 201, the macrocell 32 is connected to the input-output terminal 152 via the multi-layer wiring 202, and the macrocell 33 is connected to the input-output terminal 153 via the multi-layer wiring 203.
In FIG. 10, the macrocell 30 is connected to the input-output terminal 150 on an outline 120 nearest the macrocell 30 via the multi-layer wiring 200. In the same way, the macrocells 31 to 33 are connected to the input-output terminals 151 to 153 on the outline 120 nearest these cells.
When routing functional blocks each having a layout as shown in FIG. 10, the routing may significantly detour, resulting in an extended length of routing which impairs the signal delay characteristics.
FIG. 11 shows an example of an extreme routing detour. The semiconductor integrated circuit of FIG. 11 has functional blocks 20 to 24 closely placed each other, with the functional block 20 being connected with each of the functional blocks 21 to 24. The input-output terminal 150 of the functional block 20 is connected to the input-output terminal 170 of the functional block 24 by a multi-layer wiring 250. In the same way, the input-output terminal 151 of the functional block 20 is connected to the input-output terminal 171 of the functional block 23 by the multi-layer wiring 251, the input-output terminal 152 is connected to an input-output terminal 172 of the functional block 22 by a multi-layer wiring 252, and the input-output terminal 153 is connected to an input-output terminal 173 of the functional block 21 by a multi-layer wiring 253.
In this manner, routing among functional blocks may become complicated according to the relative positions of the functional blocks. Because semiconductor integrated circuits commonly used have several hundreds or more functional blocks, the routing connections among the functional blocks may become very complicated.
In addition, as shown in FIG. 12, some semiconductor integrated circuits use signal input-output ports 100 to 103 of macrocells 30 to 33 inside a functional block 20 as the input-output terminal for the functional block 20.
The routing of macrocells inside the functional block 20 having a configuration as shown in FIG. 12 is sometimes hindered by obstacles 50 and 51 which are formed in the functional block 20 due to congestion of the routing inside the semiconductor integrated circuit. The obstacles 50 and 51 are formed when wiring layers are subjected to some restrictions such as lack of routing resources.
An objective of the present invention is to provide a semiconductor integrated circuit having a functional block in which the degree of freedom in the placement and routing can be increased and which, therefore, can be reused as a design asset, and further to provide a method of designing such a semiconductor integrated circuit.
A semiconductor integrated circuit in one aspect of the present invention comprises:
functional blocks each of which includes an outline having at least four sides; and
a wiring layer connecting the functional blocks,
wherein at least one of the functional blocks has at least four terminals, each one of which are placed on each one of at least four sides of the outline, and
wherein all of the at least four terminals are connected to one point in the at least one of the functional blocks, at least one of the at least four terminals is an effective terminal connected to at least another one of the functional blocks, and a rest of the at least four terminals is a dummy terminal which is not connected to any other of the functional blocks.
This configuration makes it possible to select one terminal which is positioned at the most advantageous point for routing among the terminals placed on each of at least four sides of the functional block as an effective terminal when functional blocks are routed. Use of this effective terminal for connecting functional blocks can prevent a significant detouring of the routing, reduce the length of routing, and solve the signal delay problem. Terminals other than the effective terminal are dummy terminals. Because routing inside the functional block is fixed by this configuration, the electrical characteristics and signal delay characteristics become fixed and stable. Therefore, once a delay simulation inside the functional block has been performed, it is unnecessary to perform the delay simulation again when the functional block is reused thereafter. The functional block in this aspect of the present invention has increased freedom of placement and routing because the designer does not need to look for a placement in which the routing has an advantage by inverting the placement and routing in various directions.
At least two terminals among the at least four terminals of the at least one of the functional blocks may be effective terminals each of which is connected to different one of the other of the functional blocks.
The routing length may be decreased by this placement as compared with the case where routing is provided from one terminal to two functional blocks.
The at least one of the functional blocks may have the effective terminals on at least one side of the outline.
In this instance, each of the effective terminals may be connected to different one of the other of the functional blocks.
The routing length may be decreased by this placement as compared with the case where each of the two effective terminals on different sides is connected to each of the two functional blocks.
Two of the functional blocks may be located adjacent each other, and the effective terminals respectively placed on two facing sides of each of the outlines of the two of the functional blocks may be connected.
The length of the routing among the functional blocks can be minimized in this way.
Macrocells may be placed in the at least one of the functional blocks, and the at least four terminals may be connected in common to one of the macrocells.
Another aspect of the present invention provides a method of designing a semiconductor integrated circuit including:
functional blocks each of which includes an outline having at least four sides; and a wiring layer connecting various part within each of the functional blocks and connecting the functional blocks, by an automatic placement-routing device, the method comprising:
a first step of registering a definition of placing terminals on the outline of at least one of the functional blocks for connecting to other of the functional blocks in the automatic placement-routing device;
a second step of registering a net list containing a definition of connections among the functional blocks in the automatic placement-routing device; and
a third step of deciding a placement of the functional blocks and a routing among the functional blocks by the automatic placement-routing device according to the definitions which are registered in the first and second steps,
wherein the first step comprises a step of defining at least four terminals respectively placed on at least four sides of an outline of the at least one of the functional blocks, and
wherein the third step comprises:
a step of selecting at least one of the at least four terminals as an effective terminal for connecting to at least one of other of the functional blocks based on the decided placement of the functional blocks; and
a step of selecting a rest of the at least four terminals as a dummy terminal which is not connected to any other of the functional blocks.
This method ensures selection of a terminal which is most advantageous among at least four terminals existing on at least four sides as an effective terminal. Because the other terminals exist as dummy terminals, routing inside the functional block is always fixed, whereby electrical characteristics and signal delay characteristic of the functional block are fixed.
Various embodiments of the semiconductor integrated circuit of the previous aspect of the present invention can be implemented using this design method.
Further aspect of the present invention provides a method of designing a semiconductor integrated circuit including:
functional blocks each of which includes an outline having at least four sides; and a wiring layer connecting various part within each of the functional blocks and connecting the functional blocks, by an automatic placement-routing device, the method comprising:
a first step of registering a definition of placing terminals on the outline of at least one of the functional blocks for connecting to other of the functional blocks in the automatic placement-routing device;
a second step of registering a net list containing a definition of connections among the functional blocks in the automatic placement-routing device; and
a third step of deciding a placement of the functional blocks, selecting an actual terminal from the definition of the terminals, and deciding a routing within each of and among the functional blocks, by the automatic placement-routing device according to the definitions which are registered in the first and second steps,
wherein the first step comprises:
a step of defining at least four terminals respectively placed on at least four sides of an outline of the at least one of the functional blocks; and
a step of defining that at least one actual terminal selected from the definition of the at least four terminals is connected to a predetermined point within the at least one of the functional blocks, and
wherein the third step comprises:
a step of selecting the at least one actual terminal from the definition of the at least four terminals based on the decided placement of the functional blocks;
a step of connecting only the selected one actual terminal to the predetermined point within the at least one of the functional blocks; and
a step of connecting the selected one actual terminal to at least one of other of the functional blocks.
Differing from the above-described method, according to this method only a terminal which is advantageous for connecting one functional block with other functional blocks is present in that functional block and no dummy terminals are required to be present. This can eliminate unnecessary terminals and routing in functional blocks. The degree of freedom of placement and routing of the functional blocks is further increased by this configuration.